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ordering number : enn7632 13004tn (ot) no. 7632-1/16 overview the LC75700T is a key scanning lsi that accepts input from up to 30 keys and can control up to four general- purpose output ports. therefore it can reduce the number of lines to the front panel in application systems. features ? key input function for up to 30 keys. ? general-purpose output ports for up to four pins. ? a key scan is performed only when a key is pressed, and thus power dissipation is reduced. ? serial data i/o supports ccb format communication with the system controller. ? switching between the key scan output port and general- purpose output port functions can be controlled by the control data. ? the res pin is provided. this pin disables key scanning, and forces the general-purpose output ports to the low level. ? rc oscillator circuit package dimensions unit: mm 3246-tssop20 0.65 (0.33) 0.22 0.5 0.15 (1.0) 0.08 1.2max 6.4 4.4 6.5 1 10 20 11 sanyo: tssop20 (225 mil) [LC75700T] LC75700T key scan ic cmos ic any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircrafts control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. ? ccb is a trademark of sanyo electric co., ltd. ? ccb is sanyos original bus format and all the bus addresses are controlled by sanyo.
no. 7632- 2 /16 LC75700T parameter symbol conditions ratings unit maximum supply voltage v dd max v dd e0.3 to +7.0 v input voltage v in 1 ce, cl, di, res e0.3 to +7.0 v v in 2 osc, ki1 to ki5 e0.3 to v dd + 0.3 output voltage v out 1 do e0.3 to +7.0 v v out 2 osc, ks1 to ks6, p1 to p4 e0.3 to v dd + 0.3 output current i out 1 ks1 to ks6 1 ma i out 2 p1 to p4 5 allowable power dissipation pd max ta = 85 ? c 150 mw operating temperature topr e40 to +85 ? c storage temperature tstg e50 to +150 ? c specifications absolute maximum ratings at ta = 25 c, v ss = 0 v parameter symbol conditions ratings unit min typ max supply voltage v dd v dd 2.7 5.0 5.5 v input high level voltage v ih 1 ce, cl, di, res 0.8 v dd 5.5 v v ih 2 ki1 to ki5 0.6 v dd v dd input low level voltage v il ce, cl, di, res, ki1 to ki5 0 0.2 v dd v recommended external resistance rosc osc 39 k recommended external capacitance cosc osc 1000 pf guaranteed oscillator range fosc osc 19 38 76 khz low level clock pulse width t?l cl see figure 1. 160 ns high level clock pulse width t?h cl see figure 1. 160 ns data setup time tds di, cl see figure 1. 160 ns data hold time tdh di, cl see figure 1. 160 ns ce wait time tcp ce, cl see figure 1. 160 ns ce setup time tcs ce, cl see figure 1. 160 ns ce hold time tch ce, cl see figure 1. 160 ns do output delay time tdc do r pu = 4.7 k , c l = 10 pf *1 see figure 1. 1.5 s do rise time tdr do r pu = 4.7 k , c l = 10 pf *1 see figure 1. 1.5 s allowable operating ranges at ta = C40 to +85 c, v ss = 0 v note: *1. since do is an open-drain output, these times depend on the values of the pull-up resistor r pu and the load capacitance c l .
pin assignment no. 7632- 3 /16 LC75700T parameter symbol pin name conditions ratings unit min typ max hysteresis vh ce, cl, di, res, ki1 to ki5 0.1 v dd v input high level current i ih ce, cl, di, res v i = 5.5 v 5 a input low level current i il ce, cl, di, res v i = 0 v e5 a input floating voltage v if ki1 to ki5 0.05 v dd v pull-down resistance r pd ki1 to ki5 v dd = 5.0 v 50 100 250 k v dd = 3.0 v 100 200 500 output off leakage current i offh do v o = 5.5 v 6 a v dd = 3.6 v to 5.5 v v dd C 1.0 v dd C 0.5 v dd C 0.2 v oh 1 ks1 to ks6 i o = C500 a output high level voltage v dd = 2.7 v to 3.6 v v dd C 0.8 v dd C 0.4 v dd C 0.1 v i o = C250 a v oh 2 p1 to p4 i o = C1 ma v dd C 0.9 v dd = 3.6 v to 5.5 v 0.2 0.5 1.5 v ol 1 ks1 to ks6 i o = 25 a output low level voltage v dd = 2.7 v to 3.6 v 0.1 0.4 1.2 v i o = 12.5 a v ol 2 p1 to p4 i o = 1 ma 0.9 v ol 3 do i o = 1 ma 0.1 0.5 oscillator frequency fosc osc rosc = 39 k 30.4 38 45.6 khz cosc = 1000 pf i dd 1 v dd key scan standby state 5 current drain v dd = 5.5 v i dd 2 v dd output open 200 400 a fosc = 38 khz electrical characteristics in the allowable operating ranges LC75700T top view di 20 11 10 1 cl ce do res v dd os c v ss p1 ks6/p2 p3/ks5 p4/ks4 ks3 ks2 ki5 ki4 ki3 ki2 ki1 ks1
1. when cl is stopped at the low level no. 7632- 4 /16 LC75700T 50% v ih 1 v ih 1 v il v il cl di do ce t dh d1 d0 t d r td c v ih 1 v il t ch t cs t cp t ds t l t h t dh t ch t cs t cp t ds td r d1 d0 t dc 50% v ih 1 v ih 1 v il v il cl di do ce v ih 1 v il t h t l 2. when cl is stopped at the high level figure 1
block diagram no. 7632- 5 /16 LC75700T res ccb interface v dd di key scan ki1 ki2 ki3 ki4 ki5 ks1 ks2 ks3 ks4/p4 ks5/p3 p1 ks6/p2 key buffer general port control register shift reg i ster clock generator v ss cl ce do os c
no. 7632- 6 /16 LC75700T pin functions pin pin no. function active i/o handling when unused ki1 to ki5 1 to 5 key scan inputs. these pins have built-in pull-down resistors. h i gnd key scan outputs. although normal key scan timing lines require diodes to be ks1 to ks3 6 to 8 inserted in the timing lines to prevent shorts, since these outputs are unbalanced ? 0 open cmos transistor outputs, these outputs will not be damaged by shorting when these outputs are used to from a key matrix. key scan outputs and general-purpose output ports shared-function pins. ks4/p4 to ks6/p2 9 to 11 these pins can be set the key scan output ports or the general-purpose output ? 0 open ports by the control data kp1 and kp2. p1 12 the p1 is general-purpose output ports. ? 0 open osc 14 oscillator connection. an oscillator circuit is formed by connecting an external ? i/o v dd resistor and capacitor at this pin. reset input. that re-initializes the lsi internal states. this pin must be used. when res is low (v ss ) ? key scanning disabled: ks1 to ks3 = low (v ss ). ? key scan outputs and general output ports shared-function pins: ks4/p4 to ks6/p2 = low (v ss ). res 16 ? general-purpose output port: p1 = low (v ss ). l i gnd ? all the key data is reset to low. when res is high (v dd ) ? the states of the pins as key scan output pins or general-purpose output ports, must be set with the control data. ? and key scanning is a enabled. note that serial data must be transferred when res is high. ce 18 serial data interface. connections to the controller. note that do, being h i cl 19 an open-drain output, requires a pull-up resistor. i gnd ce: chip enable cl: synchronization clock di 20 di: transfer data ? i do 17 do: output data ? o open v dd 15 power supply. a voltage of between 2.7 v and 5.5 v must be supplied. ? ? ? v ss 13 ground. must be connected to the system ground. ? ? ? s
serial data input 1. when cl is stopped at the low level no. 7632- 7 /16 LC75700T ccb address a3 a2 a1 a0 b3 b2 b1 b0 kc2 kc1 0 1 0 0 0 1 1 0 do di cl ce 0 0 0 0 pc1 control data kc3 k c4 kc5 k c6 pc2 p c3 pc4 kp1 kp2 a3 a2 a1 a0 b3 ccb address: 62h kc1 to kc6: key scan output state setting data pc1 to pc4: general-purpose output port state setting data kp1, kp2: selection data between the key scan output ports and the general-purp ose output ports. b2 b1 b0 0 1 0 0 0 0 1 1 do di cl ce kc2 kc1 0 0 0 0 pc1 kc3 k c4 kc5 k c6 pc2 p c3 pc4 kp1 kp2 ccb address control data 2. when cl is stopped at the high level
control data functions 1. kp1, kp2: selection data between the key scan output ports and the general-purpose output ports. these control data bits switch the functions of the ks4/p4 to ks6/p2 output pins between the key scan output port and the general-purpose output port. 2. kc1 to kc6: key scan output state setting data these control data bits set the states of the key scan output pins ks1 to ks6. for example, if the ks4/p4 to ks6/p2 output pins are set to function as key scan output ports, when kc1 to kc3 are set to 1 and kc4 to kc6 are set to 0, in the key scan standby state, the ks1 to ks3 output pins will output the high level (v dd ) and the ks4 to ks6 pins will output the low level (v ss ). note that key scan output signals are not output from output pins that are set to the low level. note: ksn (n = 4 to 6): key scan output ports pn (n = 4 to 2): general-purpose output ports no. 7632- 8 /16 LC75700T kp1 kp2 output pins maximum number number of general-purpose ks4/p4 ks5/p3 ks6/p2 of key inputs output ports (+ p1) 0 0 ks4 ks5 ks6 30 0 (+1) 1 0 ks4 ks5 p2 25 1 (+1) 0 1 ks4 p3 p2 20 2 (+1) 1 1 p4 p3 p2 15 3 (+1) output pins ks1 ks2 ks3 ks4 ks5 ks6 key scan output state setting data kc1 kc2 kc3 kc4 kc5 kc6 3. pc1 to pc4: general-purpose output port state setting data these control data bits set the states of the general-purpose output ports p1 to p4. for example, if the ks4/p4 to ks6/p2 output pins are set to function as general-purpose output ports, when pc1 and pc2 are set to 1, and pc3 and pc4 are set to 0, the p1 and p2 output pins will output the high level (v dd ), and p3 and p4 will output the low level (v ss ). output pins p1 p2 p3 p4 general-purpose output port state setting data pc1 pc2 pc3 pc4
serial data output 1. when cl is stopped at the low level no. 7632- 9 /16 LC75700T kd3 output data ccb address a3 a2 a1 a0 b3 b2 b1 b0 kd2 kd1 kd30 0 0 0 1 1 1 do di cl ce 1 0 x : don t care kd27 x kd26 kd28 kd29 x kd4 kd3 a3 a2 a1 a0 b3 b2 b1 b0 kd2 kd1 kd30 0 1 0 0 1 do di cl ce 1 1 0 x : don t care kd27 x kd26 kd28 kd29 ccb address output data ccb address: 63h kd1 to kd30: key data x x 2. when cl is stopped at the high level note: if a key data read operation is executed when do is high, the read key data (kd1 to kd30) will be invalid. output data 1. kd1 to kd30: key data when a key matrix of up to 30 keys is formed from the ks1 to ks6 key scan output pins and the ki1 to ki5 key scan input pins and one of those key is pressed, the key output data corresponding to that key will be set to 1. the table shows the relationship between those pins and the key data bits. when the ks4/p4 to ks6/p2 output pins are set to function as the general-purpose output ports with the control data ?p1 and kp2? and a key matrix of up to 15 keys is formed from the ks1 to ks3 output pins and the ki1 to ki5 input pins, the kd16 to kd30 key data bits will be set to 0. ki1 ki2 ki3 ki4 ki5 ks1 kd1 kd2 kd3 kd4 kd5 ks2 kd6 kd7 kd8 kd9 kd10 ks3 kd11 kd12 kd13 kd14 kd15 ks4 kd16 kd17 kd18 kd19 kd20 ks5 kd21 kd22 kd23 kd24 kd25 ks6 kd26 kd27 kd28 kd29 kd30
key scan operation functions 1. key scan timing the key scan period is 288t (s). to reliably determine the on/off state of the keys, this lsi scans the keys twice and determines that a key has been pressed when the key data agrees. it outputs a key data read request (a low level on do) 615t (s) after starting a key scan. if the key data does not agree and a key was pressed at that point, it scans the keys again. thus this lsi cannot detect a key press shorter than 615t (s). 2. key scan operation the pins ks1 to ks6 are set to the high or low state by the control data. if a key on one of the lines corresponding to a ks1 to ks6 pin which is set high is pressed, the oscillator on the osc pin is started and a key scan is performed. keys are scanned until all keys are released. multiple key presses are recognized by determining whether multiple key data bits are set. if a key is pressed for longer than 615t (s) (where t = 1/fosc) this lsi outputs a key data read request (a low level on do) to the controller. the controller acknowledges this request and reads the key data. however, if ce is high during a serial data transfer, do will be set high. after the controller reads the key data, the key data read request is cleared (do is set high) and this lsi performs another key scan. also note that do being an open-drain output, requires a pull-up resistor (between 1 k and 10 k ) . no. 7632- 10 /16 LC75700T k e y o n * 2 . n o t t h a t t h e h i g h / l o w s t a t e s o f t h e s e p i n s a r e d e t e r m i n e d b y t h e c o n t r o l d a t a , a n d t h a t k e y s c a n o u t p u t s i g n a l s a r e n o t o u t p u t f r o m p i n s t h a t a r e s e t t o l o w . 5 7 6 t [ s ] * 2 1 1 2 2 3 3 4 4 5 5 6 6 k s 4 k s 5 k s 6 k s 3 k s 2 * 2 k s 1 t = 1 f o s c * 2 * 2 * 2 * 2 * 2 * 2 * 2 * 2 * 2 * 2 serial data transfer key data read request key data read key data read key data read do di key address (63h) key address ce key scan key input 2 key input 1 615t[s] key data read request key data read request 615t[s] 615t[s] serial data transfer serial data transfer key address t= 1 fosc
example: when control data kp1 and kp2 = 0, kc1 to kc5 = 0, kc6 = 1 are executed. (i.e.key scanning with only ks6 high.) no. 7632- 11 /16 LC75700T ki3 ki4 ki2 ki1 ki5 * 3 [h] ks6 [l] ks5 [l] ks4 [l] ks3 [l] ks2 [l] ks1 when any one of these keys is pressed, the oscillator on the osc pin is started and the keys are scanned. * 3. these diodes are required to reliabled recognize multiple key presses of keys on the ks6 line when state with only ks6 high, as in the above example. that is, these diodes prevent incorrect operations due to sneak currents in the ks6 key scan output signal keys on the ks1 to ks5 lines are pressed at t he same time. key data read request key data read key data read do di serial data transfer key address (63h) key address serial data transfer serial data transfer ce key scan key input (ks6 line) 615t[s] key data read request 615t[s] t= 1 fosc multiple key presses although this lsi is capable of key scanning without inserting diodes for dual key presses, triple key presses on the ki1 to ki5 input pin lines, or multiple key presses on the ks1 to ks6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. therefore, a diode must be inserted in series with each key.applications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bits and ignore such data.
system reset when the power is first applied, the state of function is undefined, so it must be initialized by res = l 1. reset methods this lsi stopprts the reset methods described below. when a system reset is applied, key scanning is disabeled, the key data is reset, and the general-purpose output ports are set to and held at the low level (v ss ). set res = h after the res = l period. and key scanning become possible by the control data are transferred. no. 7632- 12 /16 LC75700T control data transfer ks1 to ks3 output pins ks4/p4 to ks6/p2 p1 res ce undefined "l" defined notes: t1 3 10 s t2 3 10 s v il t1 v dd v dd min v il t2 v ih 1 blocks to which the reset applies. res ccb interface v dd di key scan ki1 ki2 ki3 ki4 ki5 ks1 ks2 ks3 ks4/p4 ks5/p3 p1 ks6/p2 key buffer general port control register shift reg i ster clock generator v ss cl ce do os c 2. internal block states during the reset period. ?clock generator reset is applied and the basic clock is stopped. (the oscillator on the osc pin is stopped.) ?key scan, key buffer reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled. and all the key data is set to low. then, when the control data are transferred, the key scanning operation is enabled. ?general port reset is applied and the outputs of p1 to p4 are all set to the low level. ?ccb interface, shift register, control register when a reset is applied, the control register is forcibly initialized internally. then, when control data are transferred, the lsi operates according to the control data.
3. output pin states during a reset sample application circuit * 4. since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 k is required. this pin remains high during the reset period even if a key data read operation is performed. no. 7632- 13 /16 LC75700T output pins state during a reset ks1 to ks3 l ks4/p4 to ks6/p2 l p1 l do h * 4 to the controller power supply to the controller from the controller +5 v v dd ks4/p4 ki5 ks6/p2 (p1) (p2) (p3) (p4) p1 osc * 5. * 6. * 7. when the power is first applied, it must be initialized by res = "l". the do pin,being an open-drain output, requires a pull-up resistor. select a res istance (between 1 and 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degr aded. each of the ks4/p4 to ks6/p2 pins must be set to either the key scan output port or the general-purpose output port. do di cl * 6 key matrix (up to 30 keys) ce v ss ks5/p3 ks3 ks2 ks1 ki4 ki3 ki2 ki1 used with the backlight controller or other circuit. (general-purpose output ports) res * 5 * 7 note:
notes on the controller key data read techniques 1. timer based key data acquisition (1) flowchart (2) timing chart no. 7632- 14 /16 LC75700T key data read processing yes no do = "l" ce = "l" t3: key scan execution time when the key data agreed for two key scans (615t (s) ) t4: key scan execution time when the key data did not agree for two key scans an d the key scan was executed again. (1230t(s)) t5: key address (63h) transfer time t6: key data read time t= 1 fosc controller determination (key on) key data read request key data read do di ce key on key on key address key scan key input t7 t7 t7 t7 t3 t4 t6 t5 t3 t3 t6 t6 t5 t5 controller determination (key on) controller determination (key off) controller determination (key on) controller determination (key off) (3) explanation in this technique, the controller uses a timer to determine key on/off states and read the key data. the controller must check the do state when ce is low every t7 period without fail. if do is low, the controller recognizes that a key has been pressed and executed the key data read operation. the period t7 in this technique must satisfy the following condition. t7 > t4 + t5 + t6 if a keydata read operation is executed when do is high, the read key data (kd1 to kd30) will be invalid.
2. interrupt based key data acquisition (1) flowchart (2) timing chart no. 7632- 15 /16 LC75700T key data read processing yes yes no do = "l" ce = "l" wait time of at least t8 key off ce = "l" no do = "h" t3: key scan execution time when the key data agreed for two key scans (615t (s) ) t4: key scan execution time when the key data did not agree for two key scans an d the key scan was executed again. (1230t(s)) t5: key address (63h) transfer time t6: key data read time t= 1 fosc key on controller determination (key on) key data read request key data read do di ce key on key address key scan key input t8 t8 t8 t8 t3 t4 t6 t6 t5 t6 t6 t3 t3 t5 t5 t5 controller determination (key off) controller determination (key on) controller determination (key on) controller determination (key on) controller determination (key off)
ps no. 7632- 16 /16 LC75700T (3) explanation in this technique, the controller uses interrupts to determine key on/off states and read the key data. the controller must check the do state when ce is low. if do is low, the controller recognizes that a key has been pressed and executes the key data read operation. after that the next key on/off determination is performed after the time t8 has elapsed by checking the do state when ce is low and reading the key data. the period t8 in this technique must satisfy the following condition. t8 > t4 if a key data read operation is executed when do is high, the read key data (kd1 to kd30) will be invalid. this catalog provides information as of january, 2004. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer?s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer?s products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the delivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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